The present invention relates to error handling in computing systems, for example methods and apparatus for disabling error countermeasures in a processing system.
Real-time, multimedia applications are becoming increasingly important. These applications require extremely fast processing speeds, such as many thousands of megabits of data per second. Such applications may be executed on single processing units, which are capable of fast processing speeds, as well as multi-processor architectures, which generally exhibit even faster processing speeds. Indeed, in multi-processor systems, a plurality of sub-processors can operate in parallel (or at least in concert) to achieve desired processing results.
The types of computers and computing devices that may be used to execute real-time, multimedia applications are extensive. In addition to personal computers (PCs) and servers, these computing devices include cellular telephones, mobile computers, gaming consoles, personal digital assistants (PDAs), set top boxes, digital televisions and many others.
A design concern in many processing systems is how to manage a processing error. Indeed, a processing error could affect the overall performance of the processing system and adversely impact the real-time, multimedia experience of a user. This is particularly true in a multi-processor system when the result of one sub-processing unit is to be used by other sub-processing units in order to achieve a desired result.
Hard processor errors, such as error correction code (ECC) errors, parity errors, processor hang-ups, etc., may be characterized as fatal errors or recoverable errors. Fatal errors may occur due to operating system errors, kernel errors, etc., while recoverable errors generally do not involve operating system errors or kernel errors. In accordance with conventional techniques, when a recoverable error occurs, some form of error recovery technique is employed, for example, re-booting the processing system (or re-booting a sub-processing unit in a multi-processing system) and re-executing the processor tasks from the beginning.
Under some circumstances, executing an error correction process can do more harm than good. For example, when an application program involves the processing of streaming video in a multi-media context, the execution of an error correction process may unnecessarily delay the execution of the application program. Indeed, the human eye tends to integrate video images from one frame to the next, and will often not perceive a data error in a particular frame of a streaming video clip. Thus, it may be beneficial to disable any error correction countermeasures in the streaming video context because unnecessary re-boot and/or re-execution of the given processor tasks may be avoided.
Another context in which it may be desirable to disable an error correction process is when such error countermeasures would be duplicative. For example, reference is made to co-pending, commonly assigned, U.S. patent application Ser. No. 10/849,623, filed May 19, 2004, entitled METHODS AND APPARATUS FOR HANDLING PROCESSING ERRORS IN A MULTI-PROCESSOR SYSTEM, the entire disclosure of which is hereby incorporated by reference. This patent application discloses a hardware-implemented error handling countermeasure in a multi-processing system environment. The system calls for moving the processor tasks from one sub-processing unit (in which an error has occurred) to another sub-processing unit that is capable of handling those tasks. It may be desirable to disable this technique of handling processing errors when other countermeasures are in place, such as software countermeasures, etc.
Therefore, there is a need in the art for new methods and apparatus for achieving efficient data processing that reduces any adverse affects of handling processing errors by at least temporarily disabling any error countermeasures when possible.